Patent · US Active

Method and apparatus for designing an integrated circuit

US8302036B2 · kind B2 · utility

0Cited by

9References

13Claims

0Family size

Assignees

Freeescale Semiconductor, Inc. · US
STMicroelectronics (Crolles 2) SAS · FR

Inventors

Lionel Riviere-Cazeaux · Austin, US
Ashish Rajput

Key dates

Filing date	Jan 5, 2007
Grant date	Oct 30, 2012
Priority date	—
Expiry date	May 25, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/398
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Method and apparatus for designing an integrated circuit, IC, layout by identifying one or more defects in a feature within the IC layout. Determining if an identified defect is improvable. Calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.