Compact modeling of circuit stages for static timing analysis of integrated circuit designs
US8302046B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2008 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Feb 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus, and methods of timing analysis with a multi-operating region gate model are disclosed, including modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation; in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation; and, in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation. Instantaneous output current provided by the time varying voltage dependent current source in the VCR region is responsive to time and the instantaneous output voltage of the logic gate. Instantaneous output current provided by the time-invariant voltage dependent current source in the AR region is responsive to the instantaneous output voltage of the logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.