Method for enabling multiple incompatible or costly timing environment for efficient timing closure
US8302049B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | May 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.