Overcoming laminate warpage and misalignment in flip-chip packages
US8304290B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Feb 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/048
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.