Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8304900B2 · kind B2 · utility
118Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Nov 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.