Memory circuit having memory cells with common source/drain region electrically isolated from all bit lines, system, and fabrication method thereof
US8305791B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 20, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Dec 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.