Memory cell with equalization write assist in solid-state memory
US8305798B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Dec 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an equalization gate connected between the storage nodes of the storage element. The equalization gate may be realized by two transistors in series, or as a double-gate transistor. The equalization gate is controlled by a word line indicating selection of the row containing the cell in combination with a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to a selected cell, both gates are turned on, connecting the storage nodes of the cell to one another and assisting the write of the opposite date state from that previously stored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.