Switched capacitor based negative bitline voltage generation scheme
US8305820B2 · kind B2 · utility
2Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | May 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array of memory cells, the memory device including a bitline biasing circuit for biasing a bitline during a write operation. The bitline biasing circuit operating to provide a negative biasing voltage to the bitline. The magnitude of the negative biasing voltage is inversely proportional to a memory cell supply voltage level provided at a memory cell supply voltage node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.