Memory power gating circuit for controlling internal voltage of a memory array, system and method for controlling the same
US8305829B2 · kind B2 · utility
3Cited by
77References
24Claims
0Family size
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Key dates
| Filing date | Feb 18, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Jan 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.