Patent · US Active

Semiconductor memory with memory cell portions having different access speeds

US8305834B2 · kind B2 · utility

6Cited by

3References

14Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Michael Richter · Ottobrunn, DE
Markus Balb · Munich, DE
Christoph Bilger · Munich, DE
Martin Brox · Munich, DE
Peter Gregorius · Munich, DE
Thomas Hein · Hersbruck, DE
Andreas Schneider · Leonberg, DE

Key dates

Filing date	Feb 23, 2010
Grant date	Nov 6, 2012
Priority date	—
Expiry date	Aug 9, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4087
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.