Class-based deterministic packet routing
US8306042B1 · kind B1 · utility
52Cited by
45References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 19, 2009 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Apr 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17312
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention pertain to deterministic packet routing systems and methods in multiprocessor computing architectures. Packets are analyzed to determine whether they are memory request packets or memory reply packets. Depending upon the packet, it is routed through nodes in the multiprocessor computer architecture in either an XY or YX path. Request and reply packets are sent in opposing routes according to a deterministic routing scheme. Multiport routers are placed at nodes in the architecture to pass the packets, using independent request and response virtual channels to avoid deadlock conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.