Method for fabricating semiconductor device using a double patterning process
US8308966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2009 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | May 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for performing a double pattering process of a semiconductor device is provided. The method includes forming a hard mask layer having a stack structure of a first layer, a second layer and a third layer in sequence, forming a first photoresist pattern over the hard mask layer, etching the third layer to form third layer patterns by using the first photoresist pattern as an etch barrier, forming a second photoresist pattern over the third layer patterns, etching the second layer to form second layer patterns by using the second photoresist pattern and the third layer patterns as an etch barrier, removing the second photoresist pattern, and etching the first layer to form first layer patterns by using the second layer patterns as an etch barrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.