Method of manufacturing stacked semiconductor package
US8309372B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2011 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Jan 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a stacked semiconductor package in which a plurality of semiconductor chips are stacked includes preparing a first semiconductor chip including a first semiconductor device, a first penetration electrode, and a first connection unit electrically connected to the first semiconductor device or the first penetration electrode, attaching the first semiconductor chip to a base substrate with the first connection unit interposed therebetween, forming a first rewiring pattern and a first protection layer on the first semiconductor chip by using a printing method, wherein the first rewiring pattern is electrically connected to the first penetration electrode and the first protection layer partially covers the first rewiring pattern and exposes other portions of the first rewiring pattern, and attaching a second semiconductor chip including a second semiconductor device to the first semiconductor chip to electrically connect the second semiconductor device to the first rewiring pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.