Process for packaging components, and packaged components
US8309384B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2010 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Oct 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15788
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.