Wafer stacked package waving bertical heat emission path and method of fabricating the same
US8310046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2011 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Sep 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer stacked semiconductor package (WSP) having a vertical heat emission path and a method of fabricating the same are provided. The WSP comprises a substrate on which semiconductor chips are mounted; a plurality of semiconductor chips stacked vertically on the substrate; a cooling through-hole formed vertically in the plurality of semiconductor chips, and sealed; micro holes formed on the circumference of the cooling through-hole; and coolant filling the inside of the cooling through-hole. Accordingly, the WSP reduces a temperature difference between the semiconductor chips and quickly dissipates the heat generated by the stacked semiconductor chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.