Semiconductor device and wafer structure
US8310065B2 · kind B2 · utility
6Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2011 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Apr 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.