Patent · US Active

Low-power clock generation and distribution circuitry

US8310294B2 · kind B2 · utility

4Cited by

18References

40Claims

0Family size

Assignee

Rambus Inc. · US

Inventors

John W. Poulton · Chapel Hill, US
Robert E. Palmer · Chapel Hill, US
Andrew M. Fuller · Chapel Hill, US

Key dates

Filing date	Feb 12, 2008
Grant date	Nov 13, 2012
Priority date	—
Expiry date	Feb 20, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/046
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.