Write-assist and power-down circuit for low power SRAM applications
US8310894B1 · kind B1 · utility
13Cited by
9References
14Claims
0Family size
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Key dates
| Filing date | Nov 15, 2010 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Jan 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.