Method for fabricating a high-K metal gate MOS
US8313991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2011 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Jul 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
A method is provided for fabricating a high-K metal gate MOS device. The method includes providing a semiconductor substrate having a surface region, a gate oxide layer on the surface region, a sacrificial gate electrode on the gate oxide layer, and a covering layer on the sacrificial gate electrode, an inter-layer dielectric layer on the semiconductor substrate and the sacrificial gate electrode. The method also includes planarizing the inter-layer dielectric layer to expose a portion of the covering layer atop the sacrificial gate electrode, implanting nitrogen ions into the inter-layer dielectric layer until a depth of implantation is deeper than a thickness of the portion of the covering layer atop the sacrificial gate electrode and polishing the inter-layer dielectric layer to expose a surface of the sacrificial gate electrode, removing the sacrificial gate electrode, and depositing a metal gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.