Process for fabricating a heterostructure with minimized stress
US8314007B2 · kind B2 · utility
128Cited by
4References
18Claims
0Family size
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Inventor
Key dates
| Filing date | Nov 10, 2010 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Nov 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a heterostructure by bonding a first wafer to a second wafer, with the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer, and conducting at least one bond-strengthening annealing step. After the bonding step and before the bond-strengthening annealing step, at least one trimming step is conducted in which the first wafer is at least partially trimmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.