Flexible and stackable semiconductor die packages having thin patterned conductive layers
US8314499B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2008 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Feb 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor die packages, systems, and methods therefor. An exemplary package comprises a patterned conductive layer having a first surface, a second surface, and a first thickness between its first and second surfaces; a semiconductor die disposed over the first surface of the patterned conductive layer and electrically coupled thereto; a plurality of conductive bodies disposed at the second surface of the patterned conductive layer and electrically coupled thereto, each conductive body having a thickness that is greater than the first thickness; and a body of electrically insulating material disposed on the semiconductor die and a portion of the first surface of the patterned conductive layer. A further embodiment farther comprises a second semiconductor die disposed over the second surface of the patterned conductive layer and electrically coupled thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.