Dynamic leakage control using selective back-biasing
US8314647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2011 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Jun 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of a dynamic leakage control circuit for use with graphics processor circuitry are described. The dynamic leakage control circuit selectively enables back biasing of the transistors comprising the graphics processor circuits during particular modes of operation. The back biasing levels are controlled by two separate power rails. A first power rail is coupled to an existing power supply and the second power rail is coupled to a separate adjustable voltage regulator. A separate voltage regulator may also be provided for the first power rail. A hardware-based state machine or software process is programmed to detect the occurrence of one or more modes of operation and adjust the voltage regulators for the first and second power rails to either enable or disable the back biasing state of the circuit, or alter the threshold voltage of the circuit within a specified voltage range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.