Power savings with multiple readout circuits
US8314867B2 · kind B2 · utility
3Cited by
15References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2009 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Oct 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imager with a switch circuit located between, and connected to, the pixel array and associated readout chains. In one embodiment the switch is located within the column sample and hold circuitry; in another embodiment the switch is located between the column sample and hold circuitry and the readout chains. The switch circuit ensures that signals from the column sample and hold circuitry are directed to enabled readout chains, which allows selective enabling/disabling of readout chains. By disabling readout chains, the imager's power consumption is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.