SRAM timing tracking circuit
US8315085B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2011 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing tracking circuit is configured within a functional memory array, obviating the need for a separate, standalone timing tracking circuit. A generated pulse is routed circuitously through conductors enlisted for timing purposes, to trigger switching of a test cell in the array, which discharges an associated bit line from a pre-charged high value. The pulled down signal resulting from the discharge is detected at a measurement unit to infer timing characteristics of the memory array. The timing tracking circuitry is implemented by re-purposing certain conductors, test cells and dummy cells inserting certain conductive or nonconductive regions at one or more layers or at vias between layers to alter operation of the respective conductors and cells. Cells and conductors not enlisted for timing remain available for efficient, reliable memory access performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.