Wordline voltage control within a memory
US8315123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2010 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Jan 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit 2 includes bit cells 4 selected for reading with a word line voltage upon a word line 20. Word line voltage control circuitry 26 generates a two-step word line voltage signal. The word line voltage first increases to an intermediate level at which word line transistors 12 weakly couple the bit cell 4 to the bit lines 8. This intermediate level is maintained for a first delay period. After the first delay period, the word line voltage is increased to a full rail value and this full rail value maintained for a second delay period. The word line voltage is then returned to a low level at the end of the read operation. This two-step word line voltage signal provides a better access disturb margin for the bit cell 4.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.