Multistage, hybrid synthesis processing facilitating integrated circuit layout

US8316335B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Harry Barowski · Balingen, DE
• Harold Mielich · Stuttgart, DE
• Friedrich Schroeder · Stuttgart, DE
• Alexander Woerner · Eppelheim, DE

Key dates

• Filing date: Dec 9, 2010
• Grant date: Nov 20, 2012
• Expiry date: May 13, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Multistage synthesis of hardware function operation descriptions is provided, which facilitates placement of logic cells in an integrated circuit design layout, and includes: parsing hardware function operation descriptions of a circuit to identify multiple instantiations of a type of logic function; performing, without shape restriction, a first synthesis on each logic function type identified as having multiple instantiations and producing an irregular-shaped logic unit layout for that logic function type; establishing an irregular-shaped blocking mask corresponding to a respective irregular-shaped logic unit layout produced by the first synthesis; creating a partial circuit layout by placing each irregular-shaped blocking mask multiple times corresponding to the multiple instantiations of the respective logic function type; and performing, employing the partial circuit layout, a second synthesis on the balance of the hardware function operation descriptions of the circuit outside the multiple instantiations of the logic function type.