Layout design for a high power, GaN-based FET

US8319256B2 · kind B2 · utility

Assignee

• POWER INTEGRATIONS, INC. · US

Inventors

• Linlin Liu · Fryeburg, US
• Milan Pophristic · New Brunswick, US
• Boris Peres · Jersey City, US

Key dates

• Filing date: Jun 23, 2010
• Grant date: Nov 27, 2012
• Expiry date: Nov 21, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/257

Abstract

A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa. A gate pad is disposed on the first dielectric layer adjacent the mesa. A conductive gate connect strip is located over the gate node and is in contact therewith. The gate strip is in electrical contact with the gate pad. A source via is formed…