Semiconductor device
US8319288B2 · kind B2 · utility
6Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2011 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Aug 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
The CMOS inverter coupled circuit is composed of CMOS inverters using SGTs and series-connected in two or more stages. Multiple CMOS inverters share source diffusion layers on a substrate. The CMOS inverters different in the structure of a contact formed on gate wires are alternately arranged next to each other. The CMOS inverters are provided at the minimum intervals. The output terminal of a CMOS inverter is connected to the wiring layer of the next-stage CMOS inverter via the contact of the next-stage CMOS inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.