Use of F-based gate etch to passivate the high-k/metal gate stack for deep submicron transistor technologies

US8319295B2 · kind B2 · utility

Assignees

• IMEC · BE
• Katholieke Universiteit Leuven, KU LEUVEN R&D · BE

Inventors

• Nadine Collaert · Blanden, BE
• Paul A. Zimmerman · Phoenix, US
• Marc Demand · Saint-Jean-Geest, BE
• Werner Boullart · Leuven, BE
• Adelina K. Shickova · Leuven, BE

Key dates

• Filing date: Jan 9, 2008
• Grant date: Nov 27, 2012
• Expiry date: Jul 5, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.