Stacked integrated circuit package having recessed sidewalls
US8319329B2 · kind B2 · utility
3Cited by
28References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2012 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Jan 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.