Electronic device package and fabrication method thereof
US8319347B2 · kind B2 · utility
1Cited by
4References
28Claims
0Family size
Inventors
Key dates
| Filing date | May 21, 2009 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Jan 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.