Planar multi semiconductor chip package
US8319351B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2010 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Apr 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, wherein first memory devices surround at least a portion of second memory devices; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the second memory devices; and a plurality of through electrodes arranged on the second memory devices and connecting the first and second semiconductor chips to the second circuit pattern of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.