NAND architecture having a resistive memory cell connected to a control gate of a field-effect transistor
US8320160B2 · kind B2 · utility
81Cited by
9References
26Claims
0Family size
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Inventor
Key dates
| Filing date | Mar 18, 2011 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | May 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/75
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a first select transistor, a second select transistor, and a first string of first memory cells provided between the first and second select transistors. Each first memory cell has a first resistive memory cell and a first transistor. The first resistive memory cell is in series with a gate of the first transistor. The non-volatile memory device further includes a first bit line coupled to a drain of the first select transistor and a plurality of word lines. Each word line is coupled to one of the first memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.