EEPROM charge retention circuit for time measurement
US8320176B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2007 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Nov 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each including a selection transistor in series with a floating-gate transistor, the circuit including, on any one row of memory cells: a first subassembly of at least a first cell, the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell, the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell; and a fourth subassembly of at least a fourth cell, the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.