Patent · US Active

Scan architecture and design methodology yielding significant reduction in scan area and power overhead

US8321730B2 · kind B2 · utility

0Cited by

3References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Talal K. Jaber · Austin, US
David M. Wu · Austin, US

Key dates

Filing date	Dec 29, 2009
Grant date	Nov 27, 2012
Priority date	—
Expiry date	Feb 2, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318541
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.