DVI link with parallel test data
US8321732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Nov 27, 2012 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N17/004
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.