Techniques for placement of active and passive devices within a chip
US8324066B2 · kind B2 · utility
3Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2011 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Oct 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.