Non-volatile semiconductor storage device with laminated vertical memory cell and select transistors

US8324680B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Tatsuo Izumi · Yokkaichi, JP
• Takeshi Kamigaichi · Yokohama, JP

Key dates

• Filing date: Feb 24, 2011
• Grant date: Dec 4, 2012
• Expiry date: Feb 24, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/30

Abstract

A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.