Retain-till-accessed power saving mode in high-performance static memories
US8325511B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2010 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Jan 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells of the 8-T or 10-T type, with separate read and write data paths. Bias devices are included within each memory array block, for example associated with individual columns, and connected between a reference voltage node for cross-coupled inverters in each memory cell in the associated column or columns, and a ground node. In a normal operating mode, a switch transistor connected in parallel with the bias devices is turned on, so that the ground voltage biases the cross-coupled inverters in each cell. In the RTA mode, the switch transistors are turned off, allowing the bias devices to raise the reference bias to the cross-coupled inverters, reducing power consumed by the cells in that mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.