Multi-level cell NOR flash memory device
US8325518B2 · kind B2 · utility
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2References
3Claims
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Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Apr 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level cell NOR flash memory device includes a plurality of gate lines, a plurality of source regions, a plurality of drain regions, a plurality of source lines, a plurality of bitlines, and a plurality of power lines. The bitlines each have a specific sheet resistance. A specific number of the bitlines are disposed between two adjacent ones of the power lines. Accordingly, the multi-level cell NOR flash memory device is of a high transconductance and uniformity and thereby features an enhanced conforming rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.