Structure and inhibited operation of flash memory with split gate
US8325521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2010 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Jun 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line of the selected memory cell. A control gate of an unselected memory cell in the flash memory array is grounded and a third voltage bias is applied to a word line of the unselected cell to turn off a word line channel of the unselected memory cell. The selected memory cell and unselected memory cell are configured in the memory device and are connected to different word lines. The first voltage bias and the second voltage bias have a same polarity. The third voltage bias and the second voltage bias have opposite polarities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.