Chip tester, method for providing timing information, test fixture set, apparatus for post-processing propagation delay information, method for post-processing delay information, chip test set up and method for testing devices under test

US8326565B2 · kind B2 · utility

Assignee

• Advantest (Singapore) Pte Ltd · SG

Inventors

• Michael Daub · Woodinville, US
• Alf Clement · Aidlingen, DE
• Bernd Laquai · Stuttgart, DE

Key dates

• Filing date: Aug 22, 2007
• Grant date: Dec 4, 2012
• Expiry date: May 27, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3191
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information.