Interprocessor direct cache writes
US8327071B1 · kind B1 · utility
23Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 13, 2007 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Oct 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system level 2 caches are positioned on the memory side of a routing crossbar rather than on the processor side of the routing crossbar. This configuration permits the processors to store messages directly into each other's caches rather than into system memory or their own coherent caches. Therefore, inter-processor communication latency is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.