Optimizing power management in multicore virtual machine platforms by dynamically variable delay before switching processor cores into a low power state
US8327176B2 · kind B2 · utility
3Cited by
3References
20Claims
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Key dates
| Filing date | Mar 31, 2010 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | May 20, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Distributing a thread for running on a physical processor and enabling the physical processor to be switched into a low power snooze state when said running thread is IDLE. However, this switching into said low power state is enabled to be delayed by a delay time from an IDLE dispatch from said running thread; such delay is determined by tracking the rate of the number of said IDLE dispatches per processor clock interval and dynamically varying said delay time wherein the delay time is decreased when said rate of IDLE dispatches increases and the delay time is increased when said rate of IDLE dispatches decreases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.