Integrated circuit providing improved feed back of a signal
US8327200B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2009 |
| Grant date | Dec 4, 2012 |
| Priority date | — |
| Expiry date | Sep 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (“IC”) in which a debug signal is fed back within a core block is disclosed. The core block generates the debug signal. The core block includes a hardened routing that routes the debug signal within the core block. The IC also includes a programmable routing, coupled to the core block, to route the debug signal external to the core block. The hardened routing transmits the debug signal at a faster rate than the programmable routing. Further, the IC includes a selection device, coupled to the hardened routing and the programmable routing, to select one of: the hardened routed signal or the externally routed signal. In addition, the IC includes an external debug circuit, coupled to the programmable routing, to condition the externally routed signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.