Method for fabricating at least three metal-oxide semiconductor transistors having different threshold voltages
US8329525B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 4, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Dec 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
Abstract
At least three metal-oxide semiconductor transistors with different threshold voltages are formed in and above corresponding first, second and third parts of a semiconductor substrate. The second transistor has a lower threshold voltage than the second transistor, and the third transistor has a lower threshold voltage than the second transistor. The gate oxide layers for the three transistors are formed as follows: a first oxide layer having a first thickness is formed above the first, second and third parts. The first oxide layer above the second part is etched and a second oxide layer having a second thickness smaller than the first thickness is formed. The first oxide layer above the third part is etched and a third oxide layer having a third thickness smaller than the second thickness is formed. The second and the third oxide layers are then nitrided to form first and second oxy-nitride layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.