Semiconductor device and method of manufacture
US8329552B1 · kind B1 · utility
5Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2011 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Jul 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.