Semiconductor nanowire transistor

US8330143B2 · kind B2 · utility

Assignee

• QUNANO AB · SE

Inventors

• Lars-Erik Wernersson · Lund, SE
• Tomas Bryllert · Handen, SE
• Erik Lind · Lund, SE
• Lars Samuelson · Malmö, SE

Key dates

• Filing date: Jun 16, 2006
• Grant date: Dec 11, 2012
• Expiry date: May 28, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/824
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A nanowire wrap-gate transistor is realized in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.