Frequency multiplier circuit
US8330506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2008 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Dec 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D7/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency multiplier circuit, comprising a first stage including a first differential pair of amplifier elements having respective current conduction paths connected in parallel between first and second nodes and respective control terminals connected to receive input signals of opposite polarity at an input frequency in the radio frequency range, the first and second nodes being connected to respective bias voltage supply terminals through first and second impedances respectively so that current flowing differentially in the current conduction paths of the first differential pair of amplifier elements produces a voltage difference across the first and second nodes at a frequency which contains a harmonic of the input frequency, and a second stage including a second differential pair of amplifier elements coupled at the harmonic of the input frequency with the first and second nodes to amplify differentially the voltage difference and produce an output signal at the harmonic of the input frequency. Radio frequency connections apply the voltage difference across the first and second nodes at the frequency of the harmonic to the second differential pair of amplifier elements and bl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.