System and method of transistor switch biasing in a high power semiconductor switch
US8330519B2 · kind B2 · utility
33Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Aug 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method are provided for switching in a semiconductor based high power switch. Complementary p-type based transistors are utilized along insertion loss insensitive paths allowing biasing voltages to alternate between supply and ground, allowing for negative voltage supplies and blocking capacitors to be dispensed with, while improving performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.